Research And Implement Of Convolutional Encoding Based On FPGA

As one of the pop techniques in Error Control Coding under digital baseband processor of wireless communication systems, the convolution code technique base on Viterbi algorithm has been widely used. As the main develop trend of future mobile communications, Wireless LAN is developing towards high speed,low power dissipation and facility connect. As the key technique of 4G, OFDM technique is applied in IEEE802.11 protocol to achieve high speed WLAN. As a very important section of baseband processing system in the protocol, the decode speed and power dissipation of Viterbi Deccoder has the crucial affect of the whole system.On the background of IEEE802.11 WLAN digital baseband processor, a convolution encoder based on OFDM system in the protocol is studied and implemented.In the beginning of this paper, we give the basic concepts, the basic principles and the working process of convolution encoder, then, on this basis, the RTL-level circuit of the encoder has been designed and its functional simulation has been done. After that, this paper introduces the design method with Field Programmable Gate Array(FPGA), which has been widely used in the digital circuit design currently, and we selecte Altera's DE2-70 FPGA as the hardware platform for the circuit synthesis and ananlaysis. In the end, the results of this platforn show the cost of resources and the speed of encoder of this circuit.This design's main innovational work is:(1) an improvement has been taken with four parallel computing element of the wing in add-compare-select unit to reduce the power consumption and the resource costs of the decoder. (2) in decoding process, three trace back run simultaneously, at the time of reducing power consumption, also reduce the decoding delay.This convolution encoder has been involved in the whole OFDM digital baseband in information sending and receiving, and the results show the correctness of the design in function.