Implementation And Reconfiguration Of Different Constraint Length Viterbi Decoder

Viterbi decoder is an essential component of the wireless digital communicationsystems,which is used for convolutional decoding in Forward Error Correction (FEC)schemes. Different standards specify different configurations of the convolutionalcodes,the fixed viterbi decoders don't have the flexibility to support different standards inapplication.Dynamic reconfigurable system is a new implementation method that is different fromMCU and DSPs devices .Reconfigurable technologhy has the advantages of GPP andASIC, and can provide the hardwared functional efficency and softwareprogrammability.The reconfigurable system can be programmed in both time and spacedimension.The digital logic system is the same as the original system in time dimensionand external functions, but the logic cell resources of SRAM FPGA can be implementeddifferent functions, used reapeat, the scale of the system will be decreased mostly and theavailability of the hardware resources will be improved.The reconfigurable technologhy in this paper is applid in the design of Viterbi decoder.A novel pipeline architecture of ACS module and a reasonable arrangement method ofsurvive paths are described in this paper. The decoder can support constraint length from 7to 9 , and the output of the decoder is based on one-pointer algorithm .On the basis of thenew pipeline architecture of the decoder, there are two reconfigurable methods offered inthe paper. The first is based on different parameters, and the second is the self-adaptabledynamic reconfiguration maneuver.The thought of the first method is to find outsimilarities of the decoder with different parameters, and then abstract the basic cell for thereconfiguration, which is under the control of a few parameters. The experiments show thereconfigurable file is very small and reconfigurable time is short, and such method isfeasible . The other method is based on the adaptive Viterbi algorithm.The parameters ofthe decoder can be dynamically reconfigured in response to channel noise. Simulationresults and careful analysis of the decoder stucture demonstrate that total dynamicreconfiguration technology can be used to improve performance of the decoder.The design is implemented on Xilinx FPGA platform, simulation results show that thedecoder can support different constraint length from 7 to 9, and the architecture has somesuperiority in applications of devices resources.