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The Algorithm Research And Implementation On FPGA Of Channel Coding Of DVB

Posted on:2008-09-25Degree:MasterType:Thesis
Country:ChinaCandidate:X X DingFull Text:PDF
GTID:2178360215482501Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
As the demands of Digital Video and Digital Image become more and more greater, Digital TV Broadcast and Mobile TV develop rapidly, at the same time, better digital image quality is required. From the aspect of audience, the image quality takes the most important part, but for the worse performance of transmit media as well as the incoming noise interference, the image quality inevitably decreases, sometimes even cannot play. As a result, we need Error-Correct Coding (also called Channel Coding) to insure the image quality during the transmission. In the Digital Video Broadcast (DVB) system, we make use of Channel Coding in all kinds of media, no matter Satellite, Cable, or Terrestrial Broadcast.The paper firstly makes a deep research on key technology of Channel Coding in DVB standard, then designs the Channel Coding system for digital video transmission and implement it on hardware. In the system, the interface between the channel Codec and Source has made use of Synchronous Parallel Interface(SPI), which is of strong compatibility; Also the system uses G.703 on Channel interface.G.703 interface has the feature that makes directly connection among digital communication devices, which giving a comparatively large flexibility in choosing the type of Channel.On the basis of deeply understanding of RS Coding Algorithm, Convolution Interleave, Convolution Coding/VITERBI Decoding Algorithm, this article gives a design solution for Decoding Section, which has been implemented with Spartan III series chips of Xilinx Company. In RS Decoding process, Pipeline mechanism is introduced to enhance decoding efficiency. RAM Recycling Division is applied in de-interleaver, using RAM addressing I/O operation to implement convolution interleaver/ de-interleaver. This approach has the feature that easy circuit, fast implement, little cost. VITERBI decoder use truncate decoding which increases the decoding efficiency with little influence on decoding accuracy.
Keywords/Search Tags:DVB, RS, convolution-interleave, viterbi-decoding, FPGA
PDF Full Text Request
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