The Design And Realization Of Low-power Viterbi Decoder

In the communication system of recent years, the effectiveness andreliability of signal transmission is becoming more and more important. Wealways use the way of channel coding to improve the reliability of signaltransmission. Among them, convolutional coding is a coding scheme oftenused in digital mobile communication system and deep space communications.The Viterbi algorithm is known to be an efficient method for the realization ofmaximum likelihood probability (MLP) decoding of convolutional codes.In1967, Viterbi put forward the maximum likelihood probability (MLP)decoding, it’s easy to realize the decoding if the constraint length is small.And it’s also very effective and fast. While, with the increase of constraintlength, the calculated amount、storage capacity and power consumption willhave an exponential increase. It will make the Viterbi decoder with largeconstraint length be limited in the use of digital communication, especially inthe Mobile equipment, environmental equipment and handheld device. Thepower dissipation is becoming the bottle-neck of Viterbi decoder developmentand application in wireless communication.This article is in view of the low power dissipation of the Viterbi decoderwhose constrain length is7. In terms of the current process, the device’spower consumption is mainly derived from the dynamic power consumptionresulting from signal changes. The goal of this article is make the low-powerViterbi decoder design at the algorithm level and register transfer level,reduce the dynamic power dissipation. For low-power dissipation, we mainlymake the following measures: firstly, I use the Pingpang mode in the SurvivorMemory Management Unit (SMU). Secondly, in path metric update of MetricMemory Management Unit (MMU), we adopt In-place path metric updatingmethod that reduce the memory space, and lower the power dissipation. Lastly, In the coordination of various modules, we adopted clock-gatingmethod, the enable signal is invalid in some modules when they don’t need towork, reduce the power dissipation efficiently.We use bottom up system in this article, firstly, we describe theprinciples, functions of the various modules, then, integrate them to be aViterbi decoder system. We use the Verilog hardware description language toinput the design, use Quartus||and ModelSim to simulation and synthesize,and finally implement this design on FPGA.