A Design And FPGA Implementation Of (2, 1, 9) Soft-Decision Viterbi Decoder

Convolutional code is extensively used in wireless commucations. Viterbi algorithm is a maximum-likelood algorithm for convolutional code decoding and has been considered as the best decoding algorithm for its efficiency and high-speed.The main purpose of this thesis is to implement a soft-decision Viterbi decoder on FPGA which has constraint length of 9 and code rate of 1/2.In this thesis, the theory of convolutional code and Viterbi algorithm are firstly expatiated.Then several key points which decide the complexity and performance of decoder are thoroughly discussed. On the basis of decoding algorithms and relative technologies developed in this field , a Viterbi decoder design based on FPGA is given. This design is tested on Altera EP1C20 FPGA. The major work is as following:1. In this design, soft-decision decoding is used and input symbol is represented as 2-bit code being level 4 quantified.The algorithm to compute the Euclidean distance is simplified so that it can be easily implemented by hardware circuits.2. Four Add-Compare-Select units are used in this design to form a new architecture which save the chip resources compared with full-parallel design but still meet the demand of decoding speed.A new method of implementing the path metric memory is presented in the thesis, which simplify the conresponding control circuits in the control module so that the system timing is soundly optimized.3. We take Tace-back method to output the decoded data,which saves register resources and has fewer power consumption compared with Register-change method.4. We design a testbench to implement the functional simulation and verify the design by Modelsim simulator.During the simulation,a debugging method is introduced to improve the simulation efficiency.This method is implemented by inserting monitor into the design under test.5. This design passed on-chip test on Altera EP1C20 FPGA. Its max work frequency is 110MHz, and max throughoutput is 10.3Mbps.At last, we compared the performance of this decoder with Altera IP soft core and the result prove that this decoder shares a good performance and can be used in pratical engineering.