Fpga-based Viterbi Decoder

As a important part of digital communication system, channel coding technology is applied abroad in anti-jamming and error control in digital communication for protecting communication dependability. Channel coding has two kinds: block code and convolution code. Because of good performance, convolution code is applied more abroad in satellite communications and wireless communication. IS-95, a wireless digital cellular standard based on CDMA (code division multiple access), adopts convolution code as its channel coding part. The third generation wireless cellular standard adopts turbo coding, which stems from convolution coding, as its channel coding part.There are two decoding schemes for convolution code, such as sequence decoding algorithm and Viterbi algorithm. Because of simplicity,excellent performance, Viterbi decoding algorithm is abroad applied. The Viterbi decoding algorithm, proposed in 1967 by Viterbi, and it's proved that Viterbi decoding algorithm is the maximum likelihood decoder algorithm of convolution code and it has excellent decode performance. So both in theory and in practice, Viterbi decoding algorithm is researched deeply.After reading abundance other people's research literature, I comprehend Viterbi decoding algorithm and study it deeply. Analyzing every part's function and characteristic, I improve overflow control unit's design technique to suit FPGA design and traditional register exchange survivor managing algorithm. The system use input clock as system clock and use parallel structure in system to provide flexible speed.Based on researching Viterbi decoding algorithm, I design Viterbi decoder on FPGA using QuartusII design platform of Altera to design VHDL program, synthesis, simulate function logic and simulate time logic. The simulate results verify the correctness of the design.