High-Speed Viterbi Decoder On FPGA

The FPGA implementation of a high-speed Viterbi decoder is presented in this article. Not only this design can be made a high-performance single error controller, but also can be integrated in ASIC communication chip as department of full digital receiving.Radix-4 algorithm is adopted in this article. The speed of Viterbi decoder is promoted twice than Radix-2 algorithm. Add-compare-select unit is the main bottle-neck of the speed. Full parallel structure is designed. The method is efficiently promoted the speed, although the area of hardware is increasing. In the survivor management, two parallel trace-back module is designed, trace-back algorithm is better than register-change algorithm for designing on FPGA. In order to improving the performance of decoder and reducing decode error, more decode deep is adopted in trace-back algorithm for ensure that the survivor path can combine together. FPGA based Error-Rate Detector is implemented, and error detecting and error counting are completed on FPGA.Different from DSP chip based on software realization of decoding process, FPGA utilizes hardware plat to realize the Viterbi decoder, and the speed of decoding is improved greatly. The behavior of design is described in VHDL for FPGA hardware implementation. Synthesize and FPGA implementation shows that this design is feasible. The maximal data output speed of this decoder is 60 Mbps.