Design Of Viterbi Decoder

This thesis mainly focuses on the implementation of Viterbi decoder.Viterbi algorithm is the most likelihood decode algorithm of convolution code. Viterbi decoder means the VLSI implementation of Viterbi algorithm. In the area of communication, convolution code is very popular, so how to improve the performance and reduce the power and area of the decoder is an important thing.In this paper,the Viterbi algorithm as well as its various improvements are presented. The key technologies together with the performance character of Viterbi decoder's VLSI implementation are introduced. It's difficult to deduce the needed memory space and enhance the decodeing speed.By comparing the performance of the decoder with different parameters and impemeting methods,we optimize the algorithm. The in-place path metric updating is a well-known technique for efficiently dealing with the management of path metric memory in Viterbi decoders. In this paper, we present a simple but efficient technique to reduce the number of registers contrast with other in-place path metric updating method. We also optimized the memory of Trace Back Unit. It can be implemented using a single compact memory to decrease the power of read or write operations of memory.A soft-decision Viterbi decoder based on FPGA is present. The structure of the decoder is realized with Verilog HDL. The simulation of the designed decoder is discussed deeply. The way of getting soft-decision bits is helped by Matlab. The functional simulation and timing simulation are realized with the combination of the simulation software Modelsim and QuartusⅡ. After the simulation,the result is compared with IP Core.The designed soft-decision Viterbi decoder can be used in communication systems.