Dvb-s Channel Decoder

The standards for Digital Video Broadcasting are produced by the European Broadcasting Union. They are supported by many countries. DVB-S, the standard for Digital Video Broadcast over Satellite, is adopted as the national standard in China. DVB-S FEC chip is the important part of DVB-S receiver. Some of these DVB-S FEC chips are only integrated with FEC decoding function and can't evaluate channel's quality. Other chips like ST0299 though have ability to output statistical data of error codes, they can only output one kind of statistical data at a time. This dissertation accomplishes the research and implementation of DVB-S FEC decoder integrated with error monitor, which can evaluate channel's quality and output four different kinds of statistical data of error codes while decoding is performing.In this dissertation, basic theories and specific implementation methods of Viterbi decoder, de-interleaver, RS (204,188) decoder and de-scrambler are discussed. Viterbi decoder and RS (204,188) decoder are focused on. Trace back algorithm based on software pipelining is introduced to implement the survivor path management of Viterbi decoder, which reduces resource consumption of the design and speeds up the decoding. Berlekamp-Massey iterative algorithm based on linear feedback shift register(LFSR)is adopted to reduce the complexity of RS (204,188) decoder circuit. An error monitor is designed finally, which can output four different kinds of statistical data of error codes at a time.All modules'RTL codes are written in Verilog HDL, synthesized and verified on Xilinx's XC2VP30. The entire system is online analyzed by ChipScope Pro and the outcome is correct.