Design And Optimization Of The Audio DAC Digital Path

Audio electronics market grows rapidly since the 21st century. More and more consumer electronics, such as MP3 players, PMP, require high-quality audio performance. And the realization of this performance requires high-performance audio codec chip, the research of the DAC audio system has a wide range of practical significance.This paper focuses on the digital part of the audio DAC, including oversampling digital interpolation filters andΔΣmodulator. Analyzes the oversampling technique, the principle of interpolation filters and the digitalΔΣmodulator principle, structure and stability. For the interpolation filters, first selects the appropriate digital filter, and then implements the multi-level interpolation filters according to the system specifications, finally designs, optimizes and simulates the interpolation filter in the algorithm level; For digitalΔΣmodulator, first selects appropriate structure, and determines the digitalΔΣmodulator orders and the number of the quantization bits according to the theoretical analysis and matlab simulation results, finally according to the system design specifications and consideration of the circuit area, designs, optimizes and simulates the digitalΔΣModulator .Using Verilog HDL to implement the digital part of the audio DAC; In order to save circuit area, using a variety of ways, such as the use CSD coding constant coefficient multipliers, optimizes the coefficient ofΔΣmodulator to reduce the number of multipliers, shares multiplier for implementation of the interpolation filter by time division multiplexing, etc.; In order to reduce the power consumption of half-band interpolation filter, use poly phase decomposition technique. In addition, verify the integrated system using FPGA. For the CIC filter, provides an effective compensation method, that is easy to RTL implementation.Based on the theoretical study on theΔΣDAC, specially the interpolation filter and the digitalΔΣmodulator, designs and implements the digital part of the audio DAC, and finally synthesizes and post-simulates by using the FPGA. The circuit consumes 1971 LEs and 3672bits embedded RAM, which equivalents to 30,000 logic gate. Finally, the SNR of the test result is 102.83dB, which fully achieves the desired design specifications.