Font Size: a A A

The Design Of A16-bit High-Performance Sigma-Delta ADC

Posted on:2013-08-21Degree:MasterType:Thesis
Country:ChinaCandidate:S Y ZhangFull Text:PDF
GTID:2248330371459378Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
In recent years, the rapid development of digital audio also increases the requirement of the Analog-to-Digital Converter accuracy. Sigma-Delta ADC can be relatively easy to achieve high accuracy as it makes full use of oversampling and noise shaping techniques. The purpose of this paper is to design a high-performance16-bit precision Sigma-Delta Analog-to-Digital Converter. The converter includes the modulator and the digital decimation filter, the modulator shapes the noise over the signal bandwidth, and the digital filter removes the noise outside the signal bandwidth. The main contents of this paper include:Firstly, Focus on the Sigma-Delta Analog-to-Digital Converter, introduce the structure of the converter, including the modulator and digital decimation filter, then introduce the principles of the modulator and digital decimation filter and their relevant parameters.Secondly, system-level optimization is performed on a2-1cascaded modulator topology by the use of MATLAB sigma-delta design toolbox, we get the gain factors and the inter-stage coupling coefficients by simulating the modulator,the specific parameters of each module are determined through the analysis and simulation of the non-ideal factors, including the DC gain,the gain band width,the slew rate,the saturation voltage and the thermal of the amplifier,the nonlinear of the switch and the clock jitter, using the filter design toolbox to complete the design of the CIC filter and two half-band filters.Thirdly, the circuit design of the modulator includes the operational amplifier, comparator, non-overlapping clock circuit and the switching network module, which focuses on the realization of the operational amplifier, the main circuit, the bias circuit and the common mode feedback included. The comparator is simple dynamic comparator. The design of the digital decimation filter is to code and simulate the CIC filter and two half-band filters.Finally, the layout is completed using the CSMC0.5μm mixed-signal process. The modulator uses the Cadence Virtuoso layout tools for a full-custom design, digital decimation filter is automatically placed and routed by Encounter.The signal-to-noise ratio of modulator can be achieved90dB within the signal bandwidth of20KHz, it’s area is0.2139mm2, power consumption is12.5mw. The area of digital filter is11.236mm2, and power consumption is about20mw.
Keywords/Search Tags:Analog-to-Digital Converter, Modulator, Digital decimation filter, Oversampling, Noise shaping
PDF Full Text Request
Related items