Research And Design Of Decimation Filter In16-bit Sigma-delta ADC

With the development of integrated circuits, ADCs are moving toward high-speed, high-precision and low-power. Oversampling and quantization noise shaping technologies which can increase SNR and achieve ultra-high precision outputs are adopted in Sigma-Delta ADCs. Sigma-Delta digital decimation filter with20KHz bandwidth,16bit precision and44KHz output frequency is designed in this paper. A multi-stage CIC filter and two half-band filters are used to removes the modulator output noises.Firstly, basic principles of Analog-to-Digital Converter including the sample/hold and quantization/encoding are discussed. Meanwhile, different types of ADC are compared from the aspects of functionality and accuracy and horizontal. Then the paper focuses on the principles and the overall structure of Sigma-Delta ADC. Two modules (modulator and decimation filter) are discussed in details, and the oversampling technique and quantization noise shaping technology are explained.Secondly, the design requirement and solutions are analyzed. Based on the system simulations by MATLAB, half-band filters cascaded structure is considered to be used. CIC filters of32times down-sampling and two half-band filters to complete the128down-sampling rates. Through the simulations the whole system can meet the requirements, the final output accuracy is16bit.Thirdly, based on MATLAB simulation results of the filter parameters, design RTL code module. Use the industry’s mainstream UVM verification methodology to build the reusable verification platform. By using MATLAB models as golden reference models and using random stimulus to verify the decimation filter. Verification results show RTL function is correct. And then analyze functional coverage and code coverage.Finally, the layout design is completed with the CSMC0.5um mixed-signal process. The digital decimation filter is automatically placed and routed with Soc Encounter.