The Design Of 20-Bit Audio Sigma Delta ADC

Recent years, the Sigma Delta ADC has been widely studied as its advantages on compromise in speed, accuracy, and power dissipation. The accuracy of the Sigma Delta ADC applied for Audio Application is generally about 16bit. Mature Sigma Delta ADC products with higher accuracy for Audio Application are very rare. This paper focuses on designing a Sigma Delta ADC with high accuracy applied for digital audio domain.The research status of Sigma Delta ADC has been investigated, the principle of Sigma Delta ADC is introduced, and then the advantages and disadvantages of the normal structures are analyzed. On the basis of the chosen structure, the software Simulink is utilized to set up a linear model. All the factors in the model are decided by the procedure, and then system simulations are conducted to verify the design criterion. The thesis presents a feedforward fourth order Sigma Delta Modulator. The firsr integrator is the most important module of the Sigma Delta ADC circuit, of which the operational amplifier is folded cascade, using a switched capacitor common mode feedback circuit (CMFB) to achieve a stable output common mode voltage. The last three integrators have the similar structures with the first one, while the circuit current and the device size are decreased progressively. Single-bit quantizer is a comparator, which is implemented by a preamplifier and a latch comparator in this paper. For the attenuation on the amplitude-frequency characteristic curve of CIC filter within the signal bandwidth, the thesis designs a compensation filter, effectively reduces the passband ripples by pole-zero compensation. In addition, decimation filter is realized by cascading a five-order cascaded integrator-comb filter, a compensating filter, and two half-band filters. The cascaded integrator-comb filter accomplishes a 32 times downsampling, and the two half-band filters each realizes a 2 times downsampling, the output of the Sigma Delta ADC, which is a high-rate bit stream finally downsampled to Nyquist rate.The schematic and layout of Sigma Delta ADC are designed in SMIC 0.18nm 1P6M CMOS Process. The ADC core occupies an area of only 748 x 432μm2. The post-simulation results of the Sigma Delta ADC circuits shows that 112.58 dB SNR and 18.41 bit ENOB are achieved, under the condition of 1.8V voltage supply,6.144MHz sampling rate,128 oversampling ratio, and 13.5kHz,700mV sine signal. The total consumed current is 13.4mA, and all of the design specifications are fully met.