The Design And Implementation Of Memory With Function Of Verification

SRAM is the other name of Static Random Access Memory. It is usually used as a part of cache in high-powered processors for its high speed low power and high intensity. Companying with the decrease of the size of transistor and the fall of voltage recent years, the speed and intensity are increased greatly. But the correctness of function and the stability of signal have not been verified after CMOS chip was manufactured on silicon. This is what we must affront after the size of transistor achieves a new step. The fall of voltage leads to the weakness of signals,so the traditional method of verification can not achieve our purpose after it was performed on CMOS chips. This thesis stands on the foot of this problem and lodges a new method of function verification embeded in small logic. Besides, it is used in the design of SRAM with high speed single port synchronization in 65nm process. In this thesis we will study the design of SRAM and the verification methods so that we know more characters about the design of IC in 65nm. Our goal is to optimize the design of circuits, improve the performance of chips, enhance the reliability of verification, reduce the cost of verification.This thesis mainly contributes to the following three aspects:1. We have designed one SRAM with high speed single port and synchronization by full-custom design. In order to keep the stability of SRAM in 65nm, we designed the size of transistor in crucial circuits particularly. In order to get high frequency ,we did a lot of experiments and compared the results. At last we adopted the mixed decoder and latched amplifier. The result of simulation of layout showed that it achieved our design goal.2. In traditional method of verification,some knots in the chip are not easy to detect and control. Against the disadvantage of traditional method of function verification, we get a new technique of verification according to the tightness link of every module in the SRAM. It can be properly used in the function test after circuits was taped out. At the same time,we added a redundancy line in the circuit,it can locate the error when we can not get results from the SRAM array.3. We completed all the layout work of SRAM and designed the power meshwork. The area of ultimate layout is 0.1078mm~2, the delay of writing operation is 516ps,the delay of reading operation is 526ps, the logic of Function Verification is right,it can carry out the Function Verification very well and achieve our verification goal.