A 65nm High-speed Content-addressable Memory (CAM) Full Custom Design

This design is a key module which in the high-performance and multi-core CPU independence designed by the National University of Defense Technology. The CPU is a high-performance and 64-bit microprocessor which face the flow of applications. The design frequency is 1.5GHz. In order to reach high frequency of the design requirements using the existing technology, it is not meet the design just using the semi-custom method. It must be custom design to the key modules in the critical path. After the analysis, STB (store buffer) should be the key module and it needs full-custom design. STB module includes a CAM array and an SRAM array and the external control circuit. The CAM array and the external control circuit has been designed and realized in this article.In this paper, a 64×45bits embedded CAM was carried out by full-custom design and fabricated in 65nm CMOS process. First, we completed the logic design and the function verification, then the layout design and layout verification.In the worst case(the work power supply is 1v, the temperature is 125℃), the delay of writing data in the CAM is less than 523.6ps and the delay of reading data is less than 522.66 ps, and the delay of matching is less than 318 ps. The result is reached the design target. When we called the module in DC synthesis, the timing violations of the module disappeared.Using the advanced 65nm process will reduce the Area, but will increase the line delay, and parasitic parameters will increase. Reducing the supply voltage will bring the advantages of low power consumption, but will also increase the delay. This design use accelerated matching structure and it can be read and matched in parallel which make it has great advantages in speed. Finally, this design was compared with the other design by the simulation data. Taken into account, this design has a great advantage in speed compared to other designs.