Full Custom Design And Implementation Of DCA For L1 D-Cache In 65nm Technology

With the high-speed development of integrated circuit technology, the scaling down of feature size, and continuous advancement of microprocessor architecture, chip multiprocessor and multi-level storage structure is becoming a mainstream development direction of microprocessor. However, as the storage system's speed does not match CPU's speed, storage systems become the bottleneck of the overall performance of the microprocessor. Multi-level Cache structure is an effective way to solve the single-core and multi-core performance bottleneck problem and its organizational structure and design is one of thehot topics in the microprocessor research field.X microprocessor is a single chip multi-core and multi-thread processor. Each core has a 16-Kbyte I-Cache,8-Kbyte D-Cache,64-entry fully-associative ITLB,and 128-entry fully associative DTLB that are shared by the eight strands.The multi-cores are connected through a crossbar to an on-chip unified 4-Mbyte,16-way associative L2 cache.This paper is a study about the L1 D-Cache. Based on the 65nm technology, we designed and implemented the 4-way associative DCA(128-entry andl6-byte lines)of the L1 D-Cache,completed the whole module's logic design, physical design and functional verification.For the 65nm technology, a lot of new problems come out from the chip design and verification. For logic function verification, VCS-HSIM mixed method was used to ensure correct design. In the chip's physical implementation, for the signal integrity problem, power grid and route were pre-placed in the sub-module design. By placing the power grid on the whole module, IR-drop was reduced and by widening the space between sensitive signal lines, crosstalk was reduced. Wire jumpers and double via approaches were used to improve DFM.In the 65nm technology, the typical simulation results of layout indicate that:read delay is less than 450ps, write delay is less than 550ps.Area of about 304286μm2, length and width are 862μm and 353μm respectively, the border ratio is 2.44:1,both of them achieved the design objectives.