Research And Design Of A Security Sram Testing System Based On Fpga

Static Random Access Memory (SRAM), as one of the most popular used memories, because of its characteristic of high operation speed and lower consumption, is widely used. It is commonly recognized as a kind of volatile semiconductor memory because of that the data remained in SRAM disappeared after power down. However, as the fact of data remanence in SRAM after power down discovered and the study of technology and method of attacking, the security issues of SRAM has been researched and focused on more and more. For solving the issues of data remanence, adding security strategy into normal SRAM to process the remaining data, which is defined as the security SRAM.This paper is the verification based on security strategy of security SRAM from the point of testing. The key of verification is that accurately controlling the power down time of SRAM in work and whether the security strategy working or not about handling the residual data. In this paper, two security strategies are presented which are erasing method and overwriting method.This testing solution verifies it in two ways, one is based on BIST (Building in system Testing) circuit and the other is based on read and write function. This paper designs an architecture whose controlling core is a FPGA controller and the testing flows, builds the test platform. At the same time, a high efficiency and high stabilization testing algorithm is researched.Finally, the FPGA controller is described with Verilog HDL, and simulated with Modelsim. The two security strategies erasing and overwriting are verified in Xilinx Spartan-3A develop board. The verification result shows that the testing system can verify the erase and overwrite strategies in security SRAM. So the testing system achieved the expected demand.