Based On High-speed Lvds Serial Conversion Circuit Design And Research

With the development of information technology, the amount of data transmission is more and more increasing. Due to its limitations, the traditional I/O interfaces can not meet people's needs. Low Voltage Differential Signal Transmission Technology has low noise, low power, high reliability, saving cost and strong integration capability. So it becomes a new technology to the solution of I/O interface.This paper which studies the deserializer based on high speed LVDS is under ANSI/TIA/EIA-644. On this basis, according to the function, it can be parted two main modules—the receive circuit of the LVDS and deserializer.In LVDS receiver circuit, the ESD protection circuit, rail to rail amplifier, comparator circuit, shaping-buffer circuits and fail-safe circuits transform 2.5Gbps of LVDS signals into CMOS signals. Through Simulation, the LVDS receiver circuit delay 0.45ns. The rise time is 0.04ns, and the fall time is 0.03ns ,Duty cycle is 37:36. It meets the design requirements.In deserializer, in order to meet the requirements of high speed and low clock requirements, it is wonderful to use a tree structure deserializer and register structure deserializers. Through the duty cycle of 1:4 divider(divide-by-5), tree structure deserializer and register structure deserializer, it completed down to a 2.5Gbps data into the data of 10 road 250Mbps. Through simulation, it has the correct function and it is enough to meet the design requirements.Besides, layout is researched in-depth. Discussing the matching, crosstalk, noise, parasitic effects, the latch and antenna effect, I give appropriate solutions. The design based on 1P8M 0.13μm CMOS process is completed using full-custom layout method. Layout of the LVDS receiver circuit is 74×96 ? m2 and it meets the standard of I/O. Layout of the deserializer is 80×83 ? m2. Post-simulation shows that the deserializer meets the design requirements.