Circuit Design And Layout Of LVDS Transmitter

In the information era, we need higher data transferring speed and wider data bandwidth. Further more, the reduction of the power consumption has been greatly concerned in portable systems, as the portable products become more and more popular in the world. So, we need a novel and effective solution to overcome the bottleneck of I/O interface circuit,in order to realize high-speed data transmission and low noise. Low Voltage Differential Signaling (LVDS) is a new technology developed to meet this demand.This thesis concentrates on the design,analysis,simulaiton and layout of LVDS transmitter. First, according to the protocols of ANSI/TIA/EIA-644 and IEEE P1596.3, the merits of LVDS are analyzed. Then a LVDS transmitter architecture is introduced, which is divided into four parts: LVDS transmitter,7-bit serializer, band gap current source,buffer. By comparing different LVDS transmitter schemes, we choose a suitable one to realize the circuit design. Additionally, closed-loop common-mode feedback and pre-emphasis function are added to the transmitter circuit. In the serializer, the shift registers are adopted to accomplish the serializing function. The bandgap current source and buffer are also carefully designed to meet the system's requirements.In the end, we utilize the 0.25um CMOS process to fulfill the layout design by full custom design approach. Through layout verifying and post-simulation , we hope we can sufficiently guarentee the correctness of circuits.