The Post Design Of CPPLL

PLL (Phase-Locked Loop) has developed from original Linear PLL to now widely used Digital PLL, for their ever-increasing usage in electronic system. Because of the small phase-locked error and big capture scale, Charge-Pump PLL (CPPLL) has been one ofmajor digital PLL products.However, because CPPLL is a mixed signal system, the R&D becomes moredifficult than LPLL. The constructed principle and circuit realization of CPPLL are analyzed in this thesis. The mixed signal layout design and a complete Post Layout Verification of analog IC were also proposed. Three major works are carried out in this work:. The working principle and circuit structure of CPPLL components are discussed in detail.. The design method with SMIC 0.18 for CPPLL layout including the place of digital and analog module, the deal with the noise of analog circuits and the sy mmetry design used to match components is studied.. The Post Layout Verification flow applied to both digital and analog circuits was proposed, which solved include layout parasitic extract, related software interface and debugging of circuit.As the developing of IC design and manufacture process, the board level system is integrated into a chip. SystemOnChip ( SoC) is becoming the primary trend. SoC not only promotes the system performance, but also resolves the problems of noise in board and speed because of line delay. Furthermore, the cost of system is decrease greatly. So a lot of analog circuits such as PowerOn, AnalogtoDigital Converter (ADC), and PLL are integrated in chip as one necessary part of large scale integrated circuit. One of the important R&D aspect is to perform the design of analog with CMOS integrated circuits process which is always used to develop large scale logic integrated circuits.