Design Of LVDS Quad CMOS Differential Line Receiver

In the information era,we need higher data transferring speed and wider data bandwidth.Further more,the reduction of the power consumption has been greatly concerned in portable systems,as the portable products become more and more popular in the world.So,we need a novel and effective solution to overcome the bottleneck of I/O interface circuit,in order to realize high-speed data transmission and low noise. Low Voltage Differential Signaling(LVDS) is a new technology developed to meet this demand.This thesis concentrates on the design,analysis,simulation and layout of LVDS receiver.First,according to signal transmission components and the protocols of ANSI/TIA/EIA—644 and IEEE P1596.3,the merits of LVDS are analyzed.Then a LVDS receiver architecture is introduced.And carry out on the circuit model parameters calculation and simulation analysis.At last,the layout of LVDS receiver is implemented.The main problems existed in the LVDS receiver layout design are discussed,such as the match of MOS transistor, poly resistor,noise and latch-up and so on.All circuits are simulated in Hspice and the results demonstrate that the whole chip can work with good performance.We utilize the 0.18um CMOS process to fulfill the layout design.