The Design Of A M-LVDS Receiver

With the development of communication technology, serial transmission ofparallel data becomes main stream transmission method. Low Voltage DifferentialSignal (LVDS) is a International standard applied in high speed serial transmissionfield. Because of high speed low power consumption and low cost, LVDS was widelyused in high performance computer communication display and consumer electronics,etc. The M-LVDS (Multi-Point Low Voltage Differential Signal）based on LVDS, thatsupporting the applications of multi-driver or multi-receiver sharing a singletransmission line, filled the gap in multi-point applications. On the basis of the meritsof the original M-LVDS has stronger ability of driving, lower EMI and wider inputrange. And it becomes a new researching hot spot of LVDS technology.This paper studied the structure and operating principle of M-LVDS interfacebased on the TIA/EIA-899standard, summarized and analyzed the characteristics,proposed the topology of the M-LVDS receiver. The receiver consists of5modules,namely common-mode voltage shifting circuit pre-amplifier hysteresis comparatorband-gap reference and logic controlling circuit. The Innovation and technicaldifficulties in the circuit design are as follows:For the input range of-1.4V~3.8V, a novel common-mode voltage shifting circuitusing negative feed-back technology was designed. It can move the input signal withdifferent common-mode voltage to a fixed common-mode voltage by sampling theoutput common-mode voltage and adjusting the current in the terminal resistors, at thesame time it doesn’t change the differential signals. It can simplify the post stagecircuit, thus save area and power consumption.A const-gain pre-amplifier was designed using Gm-RLstructure. TYPE-IIoperating mode was realized by generating fixed current bias in the output of thepre-amplifier. The const-gm bias circuit can modulate the bias current ofpre-amplifier to make sure that the receiver can work under different technologycorner.The traditional inner-hysteresis comparator was improved. In the comparator theinput stage and the noisy hysteresis stage were separated by current mirror, thus avoiddynamic offset brought by kick-back noise.A voltage reference with cascode structure was designed to improve the PSRR lower the output ripple brought by the power supply noise, and lower the sensitivityof the receiver on the power supply.Amid at mismatch noise antenna effect and latch-up effect, the layout of theM-LVDS receiver was researched, and also gave solution to these problems. TheM-LVDS receiver was developed in GSMC0.18μm1P4M CMOS process. Testingresults indicate that the chip has input common range of-1.4~3.8V, the fastestsignaling rate is250Mbps, and it has a typical hysteresis voltage of25mV, achievedthe design goal and provides a reference for the relevant design.