Iddt Information The Rfics Management Level Fault Modeling And Test Vectors

Radio frequency integrated circuits(RFIC) in the last decade has been extensive attention and the field of wireless communications in the rapid development and become the focus of the study and hot. RFIC test of the theory and testing methods, as well as CMOS RFIC test FET key factors governing level fault study has important practical significance.In this paper a transistor FET fault model is established by the key device of affecting the whole performance CMOS radio frequency integrated circuits. The internal FET parameters is extracted, the establishment of the correct high-frequency FET small-signal model is built. PSpice test results show that the experiments comply with the requirements of the model in the amplifier circuit. PSpice simulation of the FET parameters of failure, short fault,open fault, and input waveform of different incentives, such as square wave, sine wave, triangle wave, for testing. In the feed side of circuit generated the dynamics current of the total circuit in the circuit under test is sum of the point of fault current. Through feed-side collected data, using time-domain peak-peak and average dynamic current to determine what kind of difference Waveform make the most obvious failure to achieve kinds of failure analysis and testing for FET.The results showed that open fault, short fault, transistor parameters of fault simulation experiments in the circuit, by dynamic current testing can effectively detect the fault circuit. In the input enter the square wave, sine wave, triangle wave signal excitation, feed-side to collect different fault information, in particular the input sine wave excitation, and its most obvious fault features can be more easily collected current fault information. The experimental results show that the dynamic current testing method is feasible.