The Research Of Fault Simulator For I_DDT Testing

With the rapid development of the microelectric technique,The integration level and the complexity of VLSI improving constantly have brought the severe challenge to the existing test technology and the measuring instrument.In the early 1980's,Quiescent power supply current(IDDQ)testing method was proposed in CMOS testing.Testing method based on current testing have very good compatibility with CMOS circuits,it can detect some faults and physical defects those cannot be detected by testing methods based on voltage testing. At present testing method based on current testing has become an important CMOS digital integrated circuit testing method which has been accepted widely.In order to improve the fault coverage of the testing to meet the demands of people,the dynamic current(IDDT) testing was proposed to detect some faults that cannot be detected by other testing methods in the Middle 1990's. Therefore,as an enhancement of traditional methods of testing, the dynamic current (IDDT) testing is being paid close attention to and studied by the research field and the industrial field progressively.For the convenience of test, varied circuit chip defects caused by the production process are abstracted as all kinds of models.At present the commonly used fault models mainly consist of stuck-at fault, stuck-open fault,bridge fault, store fault,delay fault,etc.Testing methods based on voltage testing mainly aim at stuck-at fault model and have also obtained satisfactory result in research for many years.Bridge fault is tested easily by Quiescent power supply current(IDDQ)testing method.In regard to stuck-open fault that is difficult to testd by Quiescent power supply current (IDDQ) and voltage testing , it can is tested by the dynamic current (IDDT) testing.In this paper An fault simulator for IDDT testing is presented,which can detect concurrently the multi-faults.Due to the subtle error among equipment manufacturing , the gate delays of circuits are not the same but range within limits.Which induces the uncertainty of the waveform transforming time. In this paper A 5-tuples (v0 ,v1 ,f, h1, h0) is used to express the waveform of a signal line in a period and methods are given to calculate the output tuples of all the primary gates. The stuck-open fault is simulated concurrently using IDDT testing with the test pattern pairs generated above.Through detaching a pattern pair into two independent patterns, the stuck-at fault are simulated concurrently.Simulation results show better fault coverage.The...