Hardware results demonstrating the effectiveness of defect detection and fault localization using multiple supply pad based IDDT measurements

Testing a digital integrated circuit is a costly process especially those designed and fabricated in modern DSM technologies. As technology scales down, the transistor density increases without a proportional increase in the number of I/Os. This poses a big challenge to the controllability and observability of internal nodes for testing with good defect/fault coverage. With the evolution of newer methods of fabrication like dual damascene copper process for interconnects, newer defect mechanisms have started showing their prominence. Traditional methods of testing by applying logic stimulus at the inputs and observing the response at the outputs is somewhat a thing of the past. Most testing is done with the help of structures that are designed to assist testing. This form of testing popularly known as "structural test" is very commonly used in the industry and has had immense success over the past few years. However, with pushing technology feature sizes even these methods are being pushed to their limits. Testing using power supply current provides another alternative and has been quite popular in the form of "IDDQ" testing. The power supply port provides a global observation point for the IC and eases pattern generation efforts for observability. IDDQ testing has been successful not only because of its simplicity but it also provided important information about chip reliability which was otherwise unavailable from logic test. However, IDDQ has been suffering from signal to noise problems due to increase in background leakage current caused due to technology scaling. A more promising technique is using "IDDT" testing which is the "Transient Current" counterpart of IDDQ testing. IDDT has similar advantages as IDDQ and can offer more. In this thesis, we will present a few innovative IDDT techniques that can enable IDDT testing of modern VLSI chips. Variations of the proposed techniques can be applied to IDDQ testing as well to extend it capabilities. Our proposed method uses current measurements made at multiple supply ports of the IC instead of one cumulative global current which is the current practice. Measuring the individual current offers multiple advantages. In this work we will show how enhanced defect detection sensitivity can be achieved using multiple supply pad measurements and compare it with a similar global current based technique using hardware chips fabricated in IBM 130 nm SOI process. We also propose a technique that can be used for fault localization using multiple supply pad measurements. Along with detailed analysis of the sensitivities of the techniques, we also address some of the aspects of test instrumentation that will most likely have an impact on the measured currents.