Sample-and-Hold Circuit Design For High Speed Pipeline A/D Converter

The pipeline architecture is the current choice for designing high speed ADCs dueto its low power and small die area. The Sample-and-Hold(S/H) circuit is usually usedas the front end of the pipeline ADCs to avoid skewing during signal sampling. As it isperhaps the most important building block in pipeline ADCs, its speed and accuracydetermine the whole performance of the system. Based on SMIC CMOS0.35um and3.3V power supply process, a S/H circuit for a14-bit100MS/s pipeline ADC wasdesigned.In this thesis, the structure of pipeline ADC and the theory of S/H circuit arediscussed. Then a detailed analysis of the error sources is given in both the mode ofsampling and the mode of holding, and several solutions have been proposed. Thisthesis also analyzes the op-amps with different configurations in order to choose aproper op-amp for this design. Following the research of the S/H circuit, a flip aroundS/H was designed based on the requirements of the pipeline ADC. The circuit consistsof several modules, such as gain-boosted op-amp, bootstrapped switches and clockgenerator.The S/H circuit designed has been simulated at100MS/s sampling rate usingCadence Spectre simulator, and the FFT analysis using Matlab has been done. Thesimulation results show that the S/H circuit achieves79.3dB SNDR and96.5dB SFDRat analog input amplitude of2Vppat frequency of9.99756MHz. It shows that theperformance of the S/H circuit satisfies the specifications of14-bit100MS/s pipelineADC.