Time Interleaving Adc Mux To Select The Sample / Hold Circuit Design

Digital processing of signals has become an attractive option in mixed-signal systems, such as digital communication and medical instrumentation. When the input signal has a wide dynamic range, the system throughput is limited by the conversion rate of the high-resolution analog-to-digital converters (ADC). Time-interleaved ADC (TI-ADC) is an attractive way to increase the overall rate in the given technology while keeping the high resolution. However, mismatches among the interleaved channels generated undesirable spectral components and can significantly degrade the signal-to-noise-and-distortion ratio (SNDR) of the system.The mismatches between channels, including gain mismatch, offset mismatch, sampling time and bandwidth mismatch, affect the TI-ADC conversion accuracy. This paper presents the theoretical analysis of the errors caused by the mismatches, and gives the design consideration for the proposed TI-ADC.Track and hold circuit (THA), as the key block of ADC, its linearity directly limits the resolution of the whole system. The work of this thesis is to design a 400Msample/s 8-bit THA, used in 4-channel TI-ADC, in order to fulfill overall rate of 1.6Gsampel/s 8-bit target. Considering the power, area, resolution and sampling rate, our THA is implemented by open-loop architecture. In the presented design, high linearity is achieved by adopting bootstrap switch and high linearity buffer. Firstly, based on the traditional bootstrapped switch, this work shows a new high-linearity bootstrapped switch by lowering the parasitic capacitance to improve the gate voltage. Through the FFT analysis, the new switch's linearity has increased by over 9.2dB.Secondly, using the low sensitivity of gain and linearity to the exact design parameters and mismatch errors in source-follower, this work proposes a new high linearity buffer, whose DC gain error is 0.8121mV in the full scale signal range. Furthermore, when a buffer with minimal bandwidth for settling is used to save power, the buffer output no longer tracks input signals at the Nyquist frequency and a large attenuation and phase shift is present. This work inserts a switch, opening in the track mode, between THA and its load capacitance, so as to get a wider bandwidth and improve the buffer's track performance, under the same power consumption.Finally, the whole circuits has been designed and simulated in a 3.3V standard CMOS process under Hspice, and layout design in Tanner, achieving an SFDR of 71.8dB using a sample frequency of 400MHz, input-range of 1.6VPP and signal frequency of 199.8MHz, while consuming 33.66mW.