The Research And Design Of Calibration Methods For Time Interleaved Analog To Digital Converter

As the key circuit transforming analog signals into digital signals,analog to digital converters have been widely applied in mobile communications,medical devices and high-performance instrumentation.With the maturity of the fourth generation mobile communication technology,the research and development of the fifth generation mobile communication technology(5G)has becomes a major opportunity and research focus of the major suppliers in the field of communication.Super high speed analog-to-digital converters have become the key factor affecting the industrialization of 5G.In order to balance speed,precision,and power consumption,the use of parallel sampling time interleaving structure is the inevitable choice to break through the bottleneck.However,in the actual application,because the device manufacturing process factors of defects and different application environment,there are offset,the sampling time and gain mismatch errors between the channel and the channel,mismatch error will reduce the overall performance of ADC greatly,so the need for these mismatch calibration and calibration algorithm design and effective development the mismatch error is one of the difficulties in the current research hot topics is needed to solve of the TIADC design.The traditional error calibration algorithms are described in detail,and the advantages and disadvantages of various algorithms are analyzed.To eliminate the three main mismatch errors of the multi-channel time-interleaved analog-to-digital converter(TIADC),which are offset mismatch error between channel,channel gain mismatch error and sampling time mismatch error of channel,i establish the model of three mismatches systematically firstly,and analyze the influence of mismatch error on the performance of TIADC system in principle of this paper,an improved background calibration algorithm for digital circuits inside the chip is proposed.By adding a way of reference ADC and statistical accumulation,the algorithms perform correlation operation on the output of the calibrated channel and reference channel in order to extract the error information in the background,and then iterates compensation for the mismatch errors through the analog circuit,so as to achieve the purpose of calibration.Secondly,based on the mismatch error extracted,a 50MS/s 10bit DAC and error correction circuit applied to error compensation is designed.Finally,based on the 40nm technology,the entire calibration system circuit is integrated into the corresponding layout.In order to verify the effectiveness of the algorithm,this algorithm is applied to 12bit 4GSps four channel TIADC circuit,when the input signal frequency of fin/fs=0.07575,ENOB and SNR respectively after calibration from 7.8581 bits and 49.1755 dB increased to 9.7061 bits and 60.3114 dB,the calibration effect is obvious.The validity of the background digital calibration algorithm is verified.In addition,the algorithm is not strictly limited to input signal type,input frequency and inter channel calibration order,and can be extended to any number of channels.