.65 Nm Of Nor Flash Memory Technology, High Voltage Power Rail Esd Protection Circuit Design And Realization

Power supply electrostatic discharge (ESD) clamping is needed to protect the IC power supply as well as to provide convenient discharge paths for ESD currents, and thereby simplify the total design problem.This paper presents a design of high voltage (3V) tolerant power ESD clamp with PMOS structure in Intel 65nm NOR Flash Memory technology following comparison of various CMOS ESD protection circuits. A stress test is done on the wafer level for the candidate circuits ESD performance measurement with a constant current TLP system. The author also makes a discussion on the distribution of ESD circuits in full chip level based on his work experience and gives a simulation method of full chip ESD analysis with an HBM ESD circuit model.After a full consideration of ESD performance, layout size and reliability, the power ESD clamp with stacked MVT (2V tolerant) PMOS structure is used as the formal circuit in the new product. That circuit shows a comparable performance as the reference circuit in TLP test and can realize the goal of the design that clamp the power rail voltage below 6V in 2kV HBM ESD test.