Performance Improvement Of Iterative Decoding Algorithm For Multilevel NAND Flash Memory Channel

NAND flash memory with its fast read and write speed,low-cost-effective,small size,has been applied for various electronic products and data storage center in large quantities,But with the application of multi-level storage technology and the further shrinking of semiconductor technology,the flash memory cells and the cell spacing are further reduced,which greatly aggravates the interference between flash memory cells and directly affects the storage reliability and service life of NAND flash memory.At present,advanced LDPC error control codes,signal preprocessing and signal post-compensation processing technologies have been used to further improve the reliability of multi-level-cell flash memory storage,but in low-latency application scenario,it is necessary to further optimize iterative convergence speed of decoding algorithm and performance of signal processing algorithms.Combined with the threshold voltage distribution characteristics of the multi-level-cell NAND flash memory channel,this paper studies the fast iterative decoding algorithm.Further,the research on error correction technology is carried out combining the reading and writing principle of multi-level-cell NAND flash memory.By building a simulation environment of multi-level-cell NAND flash memory channel with the error control of LDPC,the decoding delay of fast iterative decoding algorithm and the performance of error correction technology are analyzed in this paper.The content and contribution are as follows:(1)Based on the physical structure,programming and erasing operation principle,data reading principle and the characteristics of the main noise,the multi-level-cell flash-memory channel simulation model is approximately established.The technology for detecting threshold voltage through the maximum mutual information(MMI)scheme is analyzed in detail.(2)The coding structure and representation of LDPC codes are introduced in brief,and several common algorithms and the strategy that can effectively reduce decoding complexity for accelerating iterative convergence speed are in-depth analysis.Finally,the above-mentioned algorithms and iteration are simulated on the AWGN channel and their performance and complexity are compared.The performance and complexity the above-mentioned algorithms and iteration are compared on the AWGN channel.(3)Based on the serial min-sum decoding algorithm,a fast iterative decoding algorithm that fuse non-uniform quantized prior probability information is proposed,and a fast iteration that fuse the probability information with incorrect threshold voltage distribution decoding algorithm is further proposed.Both of the proposed algorithms estimate the convergence speed of variable nodes by processing the channel information,which can effectively reduce the decoding delay and keep the performance unchanged.(4)In the error correction research of flash memory,by fully considering the reading and writing mechanism of NAND flash,relationship of upper pages and lower pages,and the affection of channel noises on the distribution of threshold voltage,an improve BP decoding algorithm based on parallel mechanism is proposed.In addition,in order to prevent the high reliability bit of flash memory from flipping,according to the information transmission mechanism of the BP decoding algorithm,a BP decoding algorithm that adds reliability weight to the check information is proposed to improve the error correction performance.