Design Of NOR Flash Memory Driver Circuit Based On 65nm Floating Gate Technology

Flash memory plays a dominate part in Non-Volatile Memories.To program and erase Flash memory,Flash cell should be connected with several kinds of high voltages.Charge pump circuit has some advantages such as small-area-cost and inductor-needless,so it becomes the prime choice of high voltage generator on chip.To accelerate the programming and erasing of Flash cell,the rising time of charge pump is essential.Another important problem is reducing the ripple voltage of charge pump,so that the programming accuracy will be higher.In this thesis,according to the need of NOR Flash memory,a design of word-line driving circuit and bit-line driving circuit is accomplished.In addition,an on-chip temperature detector is desgined.The main contents and innovations are as follow:1.Implement a Simulink simulation of ideal charge pump.Compare Simulink simulation with classical models and analyze the best stage of charge pump.2.Design a word-line driving circuit which includes positive-high-voltage regulator and negative-high-voltage regulator and ouputs 10V positive-high-voltage and-9V negative-high-voltage.SKIP mode is used to boost the efficiency of charge pump.Conclude the characteristic of ripple voltage of Dickson charge pump.Analyze the ripple voltage of SKIP mode and proof the relation of ripple voltage and rising time so that make an optimizing and trade off with them.Design oscillator,four-phase clock generator,level shifter and bandgap reference circuit.3.Design a new wide-load and ripple voltage reduced bit-line driving circuit which generates 3.6V with load between 0.1mA to 1mA.The charge pump is divided into 3 branchs and the regulator works in a fusion mode of SKIP mode and frequency mode.The characteristic of this circuit is reusing error amplifier.The error amplifier is a two-stage amplifier whose first stage is used as a comparator.The comparator output control signal to close 2 branchs of charge pump in light load.The second stage is used to change the operation frequency to reduce the voltage ripple.To distinguish middle load and heavy load,the control signal of one branch of charge pump is provided by hysteresis inverter,so that the other branch of charge pump can be distinguish by its double threshold.Control the current of capacitor driver continuously to adapt the load variation.The bit-line driving circuit achieves ripple voltage reduced in wide current load variarion.4.Design a temperature detection circuit.It is implemented by a PTAT current and a resister in series to provide a PTAT voltage.Then transfer voltage to 3 bits digital output by ADC.The circuit design is based on XMC 65nm float gate process.The supply voltage is 1.8V.The design environment is Cadence Spectre.In standard process,positive-high-voltage programming charge pump has 10pF capacotor load,output voltage is 10V,rising time is 307ns,ripple voltage is 154mV,power dissipation is 413mW.Negative-high-voltage erasing charge pump has 20pF capacotor load,output voltage is-9V,rising time is 1.69us,ripple voltage is 35mV,power dissipation is 651mW.Bit-line driving circuit's output capacitor is 20pF,the output voltage is 3.6V.In light load,rising time is 86ns,ripple voltage is 232mV.In heavy load,rising time is 134ns,ripple voltage is 201 mV.Power effiency is 59%in heavy load.Voltage ripple is reduced in wide current load variation.The central layout area is 0.268mm~2...