Research On 3D Flash Threshold Voltage Acquisition And Application Technology

With the development of technologies such as big data,5G,cloud storage,and the Internet of Things,the amount of data generated by mobile terminals is growing rapidly,prompting the continuous improvement of the performance requirements of storage services.The traditional HDD(hard disk drive)storage devices can not meet the storage requirements of high read-write speed and low latency.Flash memory has gradually become the mainstream storage device in the consumer market and data center because of its fast read-write speed,non-volatile and strong seismic performance.However,compared with HDD storage,the shortcomings of low capacity and high price of flash memory have become the main reasons that prevent flash memory from fully replacing HDD.In order to reduce the production cost and improve the storage capacity,flash memory manufacturers adopt many methods such as multi-bit storage and three-dimensional stacking to increase bit density.Unfortunately,as the density of bit flash memory increases,its reliability problems become more and more serious.In order to further study the causes and solutions of flash reliability problem,this paper obtains and accurately models the threshold voltage distribution in different states.It will guide us to further understand the causes of various errors,and provide theoretical and data support for the adaptation and optimization of error correction algorithm.The threshold voltage distribution of the NAND Flash chip is closely related to the number of P/E(Program and Erase)cycles,retention time and program interference.In order to explore these relationships,we developed an experimental platform that supports 3D flash memory testing.The platform can realize basic operations of 3D flash memory chips such as read,program,and erase.In addition,by setting the feature address interface,the read reference voltage of the flash memory is oriented and quantitatively shifted.In this paper,using the experimental platform and the physical characteristics of flash memory,a threshold voltage acquisition method based on affected pages is proposed.Using this method,we explored the influence of programming disturbance on the threshold voltage distribution from three aspects: programming sequence,position of attack word line and data written in attack word line.In addition,we also designed an experiment to obtain the threshold voltage distribution data under different retention time and P/E cycle times through a large amount of wear and high-temperature accelerated residence on the chip.Then,using the polynomial method and BP neural network method to model the relationship between the threshold voltage distribution of each logic state with the dwell time and the number of P/E cycles,and the prediction performance of the model was compared and evaluated.Finally,the two models were used to calibrate the read reference voltage and compare the effect of read reference voltage optimization on the reliability improvement of flash memory.The prediction results of the two models show that the BP neural network model established in this paper can predict the threshold voltage distribution of flash memory blocks in different states with high accuracy.Using two models to optimize the read reference voltage can effectively reduce the flash memory error rate.Among them,the optimization effect of the BP neural network is more outstanding,especially for the heavily worn blocks,the bit error rate can even reach a 68.7% drop.