Research On High-Speed Serial Link Based Memory Interface Design And Its Application

As the basis of portable devices,embedded Flash memory occupies a large market share in the memory market.Since test cost is an importantfactor affecting chip cost,method of reducing the test cost of Flash memory is helpful to reduce the cost of Flash memory.The author of this paper proposes an improved March-like algorithm,which effectively improves efficiency and fault coverage of fault test and reduces test cost,design corresponding Flash Built-in Self Test circuit.The algorithm adopts the checkerboard vector,so that each storage cell can be maximally affected by programming operation of the surrounding storage cells,which is conducive to activate cumulative fault of the storage cell and detecte fault cell.The algorithm was tested and verified on the T5781 test machine of Avender company.The verification results show that compared with March-like algorithm,improved March-like algorithm effectively improves the efficiency by 33%.In the field test of 160 chips,no fault chip was detected in the test using the March like algorithm,while 3fault chips were successfully detected in the test using the improved March like algorithm,further proving the effectiveness of the algorithm.This topic is based on improved March-like algorithm to complete the design of Built-in Self Test circuit.The test circuit is mainly composed of three main functional modules,which are normal work mode module,test work mode module and fault test mode module.The Verilog design,synthesis and complete physical design of the circuit were completed.This design adopts the 55nm CMOS process,occupying a chip area of 15557um~2.Compared with the Flash circuit using this test circuit,the area occupied by Flash BIST accounts for about 11%of the Flash circuit.The design has been successfully applied to a mass production chip,the product is about to tape out.