Research On Low Power High Voltage Circuit Design And Fast Programming Algorithm For 65nm NOR MLC Flash Memory

With the development of IC from sub-micrometer era to nanometer, and the emerging of the MLC storing technology, flash memory is facing the key challenges of cell size scaling down, such as the floating gate to floating gate coupling, the random telegraph signals (RTS), the decreasing of the number of electrons stored in the floating gate, and the short channel effect, which increase the difficulty for Multi-Level-Storage technology. Meanwhile, the rapid development of applicateion market requires the high-density, high performance, and low power Flash memory with more functionality. How to solve the above mentioned problems on this sophisiticaed SOC are the hot topics in flash memory design.All the flash memory functionalities are highly dependent on the high voltages. The powerup management, the standby management and the read/ program/ erase control schemes are the high voltage management schemes on flash memory system. In this dissertation, how to improve the program throughput, how to reduce the standby power and how to design the powerup management scheme are discussed. The improvements are proposed and implemented based on analysis.Firstly, this dissertation provides a power-up scheme which applied in the first HDSIM card. The experiment result exhibits, this new power-up scheme can work properly under 12 modes, and more importantly, it significantly reduces the peak current from 92mA to 49.72mA, which meets the HDSIM specification now.Secondly, an adaptive standby management scheme is implemented in this dissertation. It will shut off the pump and the regulator once the leaky nodes achieve target voltages. Compared with the traditional implementation, it will shut off the refresh based on the process, voltage and temperature, which will save the power consumption further. Experiment results show that the new scheme will save 8% power consumption when compared with the traditional scheme.Meanwhile, this dissertation presents the implementation of improving MLC NOR flash memory program throughput based on Channel Hot Electron (CHE)temperature characteristic. Temperature self-adaptive programming algorithm is proposed to increase the I_g according to on-die temperature. Experimental results show that the program throughput increases significantly from 1.1MByte/S without temperature self-adaptive programming to 1.4MByte/S with proposed method under room temperature. It presents a 30% improvement.As the key high voltage component in flash memory, the charge pump is analyzed in detail for low power application. The design methodology, the key design specifications, the simulation model and the consideration of layout are all addressed in this dissertation.Although all of above mentioned is based on the 65nm MLC technology, it can also benefit other flash technology. Furthermore, the proposals and improvements in this dissertation can be used for further improving the program throughput and reducing the power consumption in Flash memory design.