High-speed Low-cost Reconfigurable Fft Processor Design And Implementation

Reconfigurable computing has become a rising technology of a great deal of research. Its hardware structure can be reconfigured as needed. It combines the best of ASIC and microprocessor by achieving high performance as the former while retaining much of the flexibility as the later. At present,research work about reconfigurable computing are mainly composed of the investigations on FPGA-based reconfigurable systems, which use less hardware resources to achieve more complex logic circuits and improve the processing speed while obviously reducing the system cost.As a powerful measure for digital signal process, Fast Fourier Transform (FFT) has been widely applied to the areas of signal analysis, wireless communication and frequency spectrum estimate, etc. Since in different scenarios there are different data point numbers needed to be processed by FFT, the FTT processor should be reconfigurable and adaptive for the change of function. So, it's important to research on how to implement the reconfiguration of FFT processor with higher speed and more flexibility while not increasing the cost of resources. Partial reconfiguration technology allows one certain module in a reconfigurable logic device to be configured, while other modules in the device remain uninfluenced. Using partial reconfigurable technology to implement reconfigurable FFT processor can improve resource utilization, reconfiguration speed and system performance.In this paper, we design and implement a reconfigurable FFT processor based on FPGA using partial reconfigurable technology. First, we make comprehensive survey on literatures about reconfigurable systems, understand their designing ideas and the basic concept and theory of FFT, and choose appropriate FFT algorithm and hardware fabric of FFT processor when our scheme is implemented. Second, based on analysis on the features of FPGA architectures and FFT algorithms, we make deep studies on fabrics of FFT processors, then, targeting on partial reconfiguration, we propose a novel reconfigurable FFT processor fabric, which can process signals with different point numbers from 32 to 1024. Third, we scheme the whole architecture of the FFT processor based on modularization designing methodology, plot out the reconfigurable modules apart from fixed modules, and accomplish designing on each module. Forth, according to the flow of module-based partial reconfiguration we accomplish design and implementation of our reconfigurable FFT processor. This processor has the function of part reconfiguration that can improve the resources utilization and degrade the reconfiguration time. Finally, we develop experiments on Xilinx Virtex-II Pro FPGA, and results show that compared with Xilinx FFT IP Core, the proposed FFT fabric can save 16%～21% resources in slice while increase 10%～30% processing speed in clock frequency and decrease 56～116 cycles of delays from input to output, indicating a remarkable higher computing efficiency. However, power consumptions of IP Core and our fabric are similar. So the proposed novel reconfigurable FFT processor in this paper is suitable for digital signal process with high-speed and low-cost.