Verify The Design And Realization Of High Performance Digital Soc Chip

Along with the decreasing of the level of process technology and the increasing of the scale of the design products, it's more difficult for verification in IC design. How to make sure of the accuracy and consistence of a design works? How to offer users the most convenient way of vericiation? It is the big problem verification engineers must solve, as well as the critical issue about the success of a chip design.In the process of IC technology development, methodology of verification design is the significant direction. IC design verification methodology takes all the verification technology into account, producing a perfect solution. With the increasing of competition in IC market, it raises a lot of additional request for verification. Moreover, it is the automation level and efficiency of verification considered as important indicator of judgment. This dissertation firstly represents the whole procedure of digital SoC design, and describes the major verification technology. Combining with the specific project,'radar signal processing SoC chip'design, the dissertation includes works which are Functional Verification, Static Timing Analysis, Formality Verification, Dynamic Verification and Design for Test and so on.The chip is a 750 million Gate-Level SoC chip. It embeds DSP and other IP cores, adopting PBGA609 package technology. In August 2007, this chip was approved in hardware verification by Ministry of Information Industry, and all the performances are functional. In December 2007, this chip was approved in technology appraise by experts of PLA General Armament Departmen, given the identity that the technology has achieved the international advances level.In the dissertation, we make a deep research on the key technology in digital IC design such as Functional Verification, Formal Verification, Static Timing Analysis, Dynamic Timing Analysis and Design for Test.Based on the key technology, we have finished the verification work of a 750 million gates circuits.That is a self-dpendent Radar SoC chip in UESTC.The main works can be summarized as follows:(1) Building of an automated verification platform and Functional Verification; (2)Formal Verification of Radar digital signal processing SoC chip;(3)Static Timing Analysis in SoC design and the static timing analysis process of Radar digital signal processing SoC chip;(4)Design for Test of Radar digital signal processing SoC chip.