Study On SoC Functional Verification

Techniques of System-on-a-Chip (SoC) based on Ultra Deep Sub-Micron technology and IP core reuse are the international development trend of the VLSI and the mainstream of IC techniques in this century. With the continuously advancement of chip fabrication technology and the exponential increase of design scale, the verification ability has fallen behind the design ability and it is becoming the bottle-neck of manufacturing chips with more complex function and larger scale. Study on SoC functional verification is done in this dissertation whose background is the design of SoC603. Tasks having been done include several aspects as follow:Firstly, functional verification techniques widely used in current SoC design are summarized. Corresponding to the top-down design flow of SoC603, the verification strategy is given. During system design phase, system-level verification in function and performance is carried out for algorithm estimation, system architecture selection and hardware software partition. During HDL coding phase, functional verification of every block is separately carried out through simulation. Chip-level verification is carried out through hardware/software co-verification after integration. A prototyping platform based on FPGA and general-purpose MCU is created on which the system-level verification of SoC603 is carried out fleetly.Then, pivotal problems in traditional simulation are analyzed. A verification environment based on Specman Elite platform is created for the verification of Special Use Communication co-Processor integrated in SoC603. Automatic constraint-random test generation and automatic test result checking which improved the verification efficiency are implemented. Coverage scale mechanism which combines code and function coverage ensures the verification sufficiency.Finally, advantages and implementation strategy of hardware/software co-verification are analyzed. Several popular approaches of co-verification are summarized. A co-verification environment for SoC603 is created and verification steps and debug method that adapt to it are given. Performance of SoC603 is improved by eliminating some bugs found with co-verification.Techniques studied in this dissertation had already been employed in functional verification of SoC603 and the chip design has already been taped out.