Crosstalk fault test generation and hierarchical timing verification in VLSI digital circuits

Recent submicron design technologies for microprocessors push clock speeds up to 1 GHz. However, there are unexpected factors constraining further improvements in performance, such as increased interconnect delay and cross coupling noise. The conventional approaches of timing verification for high speed circuits may not be valid due to unexpected side effects. Therefore, there is a need for an efficient methodology to test crosstalk and timing verification for high speed circuits.; Crosstalk effects may be provoked when two or more interconnect lines run in parallel for some minimum distance so that a signal transition on one line affects the signal on the other. We developed a new algorithm, ATEG (Automatic Test Extractor for Glitch), for generating test vectors for crosstalk glitch tests. The results show that ATEG efficiently generates test vectors to create a glitch at candidate nodes and propagates the glitch to latches or primary outputs.; An efficient methodology for testing crosstalk faults on critical paths was also developed. Using the critical path analyzer, CRITIC, we generate test vectors for crosstalk faults on critical paths by adding dummy-delay buffers with “AND” or “OR” gates.; We developed a new approach for finding the critical paths in a dynamic circuit and generating test vectors for delay tests of the circuit, given information on path delays of unit cells. We use path gates, function gates, and static gates to represent discharge paths in a dynamic circuit. We developed the path gate extraction tool (PEAR) to construct the path gates, function gates, and static gates. CRITIC identifies the critical paths and generates test vectors for delay tests of the integrated units. The methodology was successfully applied to industry circuits for identifying the critical paths and generating delay tests.; We also developed the Instruction Space Search (ISS) technique for hierarchical timing verification which searches the instruction space to verify that the worst case paths in an embedded module correspond to true paths at the chip level. ISS provides an efficient methodology for timing verification and manufacturing delay tests at the chip level. Both crosstalk fault tests and delay tests in an embedded module can be extended to the chip level using the ISS approach.