Applied Research, The Adc In The System Chip

SoC (System-on-a-Chip) is the trend of VLSI technology. A signal processing system which contains sample, conversion, storage, processing and input/output of signal can be realized in a single chip. In this system, converting analog signal to digital signal plays a very important role. With the rapid development of SoC technology, Analog-to-Digital Converter (ADC) module is becoming increasing crucial and the desire of ADC IP core is also becoming more exigent than before.Firstly, a brief description of SoC technology, analog IP core and the history of A/D converter are given in the thesis. Then the structures and performance parameter of ADC are discussed. In following chapter, the design flow of a 10-bit successive approximation register A/D converter which include three important submodules: DAC, comparator and SAR register is provided. For standard digital interface and more configurable functions, some digital modules are designed around the SAR ADC which mostly consists of analog circuits. These digital modules include A/D result register, control register and some assistant circuits outside of ADC IP core. Finally, the thesis introduces the low cost design method of the digital modules, which is called the sleep mode.When the circuit design is completed, the mixed-signal simulation of ADC IP core is carried out by Spectre-Verilog in Cadence developing environment. The simulation results prove that the ADC can achieve 10 bits resolution. Its Offset error, gain error, INL and DNL are less than±1LSB with 5V power supply. The power consume simulation also proves that the noise of the digital modules decreases and the precision of A/D conversion grows up when ADC works in sleep mode.Based on CSMC 0.5μm DPDM with OTP cell, P-sub, twin well process, the layout design and physical verification, such as DRC and LVS are completed. The ADC IP core introduced above is already integrated in an 8-bit MCU and attend CSMC MPW project.