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Asic Design Of Digital Down Conversion Decimation Filter Group

Posted on:2008-11-28Degree:MasterType:Thesis
Country:ChinaCandidate:Y O ChenFull Text:PDF
GTID:2208360212475352Subject:Communication and Information System
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Digital Down-Converter (DDC) is one of the key technologies in Software Defined Radio. Its basic function is to pick up useful narrowband signals from high-speed medium frequency digital signals and transform them to base band. Afterwards, the low-speed base-band signals can be processed by DSP devices.The Decimal Filter Group is a key module of Digital Down-Converter. Through decimating and filtering, it slows down the signal rate to meet the requirements of following modules. Decimating in time domain causes signal frequency spread and alias. Therefore, anti-alias digital filters are required. And their performance determines the effect of signal rate transformation.This dissertation introduces basic theories and architectures of DDC and summarizes some key algorithms such as CORDIC Algorithm, Distributed Arithmetic, Re-sample Theory, Feedback Theory etc.After introducing the principals of the CIC filter, HB filter and FIR filter which form the Decimal Filter Group, this dissertation proposes some new architectures of the HB filter based on folding technology and multiplexing, and FIR filter based on Distributed Arithmetic to reduce power consumption and save hardware resources.By studying the algorithms of the filters, this dissertation works out RTL implementation architectures of the CIC module, HB module and FIR module.This dissertation discusses some important issues about the ASIC design of the DDC chip, including design of reset signals and RAM, synthesis, Design for Test, static timing analysis and place & route.The last part of the dissertation presents system modeling, FPGA verification and ASIC chip test, and shows the testing results.The algorithms and chip design techniques discussed in the dissertation have been implemented in the DDC chip design project which the author takes part in. Based on 0.13 micron-meter technology, the DDC chip works on a high performance and meets all requirements. The research fruit of ASIC design of DDC based on this dissertation is of important theorical and economical value and can be applied to many purposes.
Keywords/Search Tags:Digital Down-Converter, Digital Filter, Folding Technology, Distributed Arithmetic, ASIC Design
PDF Full Text Request
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