FIR Digital Filter&Data Synchronization Design And Implementation On FPGA In Digital Substation

The application of Merging Unit (MU) becomes more and more widely with the rapid development of digital substation. In digital substation, on one hand, the sampling data of MU need to guarantee certain precision, and contain higher harmonic frequency components so that the data can be provided to the following measurement and protection units and so on. But there exists a question that protection device of Intelligent Electronic Devices (IED) receives the sampling data which need not contain high harmonic. On the other hand, the data of multiple MUs from the digital substation transmit to protection device, but sampled data of each MU are not always at the same moment, and protection device receives the data which must be high synchronicity. There is an issue that the protection device obtains the data of MUs from the sampling data synchronously. In order to solve the above problems, the research of the digital filter, data synchronization and implementation on FPGA will be integrated in this thesis. The specific tasks are as follows:(1) The basic principle of FIR digital filter is introduced, which focuses on Distributed Arithmetic (DA) of the digital filter and the optimized DA is analyzed. Meanwhile, the basic principle of data synchronization is also introduced, which analysis the theoretical maximum error of algorithms of Linear data synchronization, Newton data synchronization and Parabola data synchronization.(2) The DA of the digital filter adopts FPGA implementation based on Verilog language. The top to down hierarchical structure and the independent modular are used in the whole design. What’s more, the optimized algorithms of OBC coding and multiple look-up tables based on DA are utilized. Finally the results of FPGA implementation and the simulation results of Matlab are analyzed to verify the correctness of the digital filter design.(3) The Linear data synchronization. Newton data synchronization and parabola data synchronization are also implemented by using FPGA based on Verilog language. The three algorithms make use of the basic multiplication module and division module, and the evolved modules based on the two basic modules to implement these algorithms. Then, the results among these algorithms are compared to find out scopes of their applications. Finally the FPGA results and Matlab simulation results are discussed to prove the correctness of the data synchronization design. (4) By integrating the digital filter with data synchronization, the big Merging Unit scheme is proposed. Digital filter and Linear data synchronization, Newton data synchronization and parabola data synchronization are combined together respectively and realized on FPGA. The results among these integrated algorithms are compared, which verify the design of these big MUs what can meet the requirements of amplitude precision and time accuracy in digital substation. The results show that the big MU can realize the sampled data’s digital filter and data synchronization.