The Design Of S/H Circuit Of12bit100MHz Pipeline ADC

In recent years, with the rapid development of multimedia technology and the Internet of Things technology, high-speed high-precision analog-to-digital converter (ADC) has become increasingly important. High-speed, high-precision sample/hold circuit (S/H) is a core component of the ADC. This paper carried out a detailed study on the high-speed, high-precision sample/hold circuit (S/H), and focuses on analysis and design of the bootstrapped switch and fully differential operational amplifier (OTA). Finally, completed whole sample/hold circuit for high-speed, high-precision12bit100MHz Pipeline ADC.First, in order to improve the accuracy of the S/H circuit and reduce the chip area, select the flip-style capacitor sample/hold circuit. After analyses the three major sources of error of the Sample S/H circuit, I determined the design focus of this paper is to solve the switch linearity problem and the high gain and wide bandwidth fully differential op amp. Then, taking into account the gate voltage of the bootstrap switch can effectively solve the switch linearity problems, so I designed a linear bootstrap switching circuit. Taking into account the importance of high gain and wide bandwidth on the sample/hold circuit in the process of establishing, therefore, the two gain bootstrap telescopic fully differential op amp with high gain, wide bandwidth had been designed. Finally, use Virtuoso to complete the layout of each module circuit.Under Linux working environment, based on SMIC0.18um CMOS technology library, using the SPECTRE tools of Cadence on finished all the modules’simulation. The results show that the gate voltage bootstrapped switch is designed to achieve a good level to follow. The design of the fully differential op amp achieved94dB high gain,1.2GHz wide-bandwidth, phase margin of74°. Sample/hold circuit unit work well under a1GHz clock frequency and100MHz input signal, Reached the application requirements of the12bit100MHz Pipeline ADC circuit.