.e1/vc-4 Mapping The Demapping System Design,

After telecom communicaton's style changed from analog to digital, the communication mode had been PDH (Plesiochronous Digital Hierarchy) .At present, as the modem telecom technology is progressing rapidly, the PDH communication mode appears many disadvantages, and this mode can't adapt requests of information times to the telecom network. And in this condition, it becomes necessary to the appearance of SDH in telecom communication.SDH (Synchronous Digital Hierarchy) is the new transmission mode which combines high speed and big capacity fiber transmission technology with intelligent network technology. Because of its high flexibility and manageability, now SDH has become an important development direction of fiber communication.In SDH the basic transmission signal is the first level module STM-1 (Synchronous Transport Module) which can carry many kinds of operation signals in large scope rate levels. And the N numbers of STM-1 can form higher rate STM-N signals with byte interleaved. Just the operator of telecom can not give up all the existing PDH network, so the SDH must compatible with PDH.The 2.048Mbit/s tributary E1 (Electrical interface signal) is the basic rate interface in public network, so the realization of tributary El add/drop with STM-1 is the important part of SDH compatibility with PDH.E1/VC-4 Add/Drop system can realize four tributary El signal asynchronous add/drop with VC-4, the system can support El signal with HDB3 or NRZ code. The system can be used as ADM, TM, Dual-Single ring and Single-single ring.This thesis introduces the whole design scheme of E1/VC-4 mapping/demapping system, and also shows the division of function and module. This design adopts the design method of Top-Down which is used broad in ASIC design today, and using hardware description language Verilog as inputs designs the circuit modules. Then these module will be processed function simulation with VCS, and should be synthetized with Design Compiler(VCS and Design Compiler are products of Synopsys Corp), then the verification of FPGA with these modules is done in the platform of Altera FPGA device EP1C6T144C8 (Cyclone series) .