Design Of C-4/VC-4 Mapping And Demapping System In SDH

With the development of modern digital communication technologies, the traditional Plesiochronous Digital Hierarchy (PDH) is becoming an obstacle to the further development of optical fiber communication technology because of the weaknesses exposed in application of the digital communication. In this case, the Synchronous Digital Hierarchy (SDH) is gradually replacing PDH as a major transmission network system with the advantages of its unified international specification, unified standard interface, high transfer rate, large transmission capacity,good compatibility,powerful network management capabilities and so on. Besides, SDH was more and more widely used in optical communications, microwave communications and other technical fields.In this paper, On the basis of the theoretical analysis, we design a solution of SDH mapping and demapping system based on FPGA. The purpose of the study is to map the slip signal of 139.264Mbit/s into VC-4 through C-4 as well as to demap VC-4 and recovered the original signal. System functions is achieved by the FPGA chip. This paper selected Altera's CycloneⅢseries EP3C25Q240C8 chips. The full text includes the following main elements:Firstly, we introduce the weakness of PDH, the advantages, the frame structure, and the basic multiplexing unit of SDH as well as basic structure and methods of multiplexing and mapping of SDH. Secondly, according to the theoretical of SDH, we select an appropriate mapping method and use the top-down design concept to divided the whole system into eight modules(among this, each of the mapping module and demapping module is divided into four submodule):HDB3 coding/decoding module, serial signal/parallel signal conversion module, positive rate justification module, rate recovery module and mapping/de-mapping module. Once more we use Verilog HDL to design the circuit module and make functional simulation, synthesis, layout, and timing simulation, until timing simulation results meet with our requirements,then download the file to the chip through QuartusⅡand test the result through Oscilloscope and BER Tester (ANT-5). Finally, the papers are summarized, and prospects for future research is be made. The paper aims to research the C-4/VC-4 mapping and demapping part of SDH and design a solution for the system through FPGA technology.At the same time prepare for aligning and multiplexing of SDH in the next step. The design results of this paper is in order to lay the foundation for forming the transmission network of SDH (STM-N).