Sdh E1/vc-4 Complex Demultiplexing System Design And Implementation

As the new generation of transmission technology, SDH (Synchronous Digital Hierarchy) possesses many superior features, such as global uniform stardard interface, intelligent circuit allocation and network administration, high reliable self-stabilization, high speed, vast capacity and low cost. SDH had rapidly replaced PDH (Plesiochronous Digital Hierarchy) and became the dominant transmission network system. Now SDH is a leading technology in fiber communication and is increasingly broadening its reach to client access network.The basic transmission signal is STM-1 (Synchronous Transport Module-1), which can carry various traffic and support a large range of signal rates. N STM-1s make up a high speed STM-N signal by byte interleave and multiplexing. Since the existing PDH network can not be wholly abandoned during a short period, SDH networks need to coexist with PDH networks. Consequently, the effective compatibility with PDH is an essential consideration of SDH, and node in SDH network must provide access ability for PDH singal in multiple rate level. Because E1 (Electrical Interface Signal-1) is the primary and pervasive interface in public telephone network, realizing El signal's adding to/dropping from STM-1 signal is very important for compatibility with PDH.This paper studies the E1/VC-4 multiplexing/demultiplexing system, which can support multiplexing four tributary El signals into a VC-4 signal or demultiplexing VC-4 signal and restoring El signal. The coding format of E1 can be HDB3 or NRZ. This system can be used in SDH node facilities such as ADM, TM, Dual-unidirection ring and single-unidirection ring.This paper presents a whole design scheme of E1/VC-4 multiplexing/demultiplexing circuit from system-level perspective. The funcition definition and module partition is discussed. This design adopts the Top-Down design method which is used widely in ASIC design industry. Verilog HDL is utilized as description and test approach through this design. Simulation and validation is performed on Synopsys Corp.'s EDA platform VCS, logic synthesis is implemented using Design Compiler, danymic timing simulation is executed using QuartusII. Finally FPGA physical verification is completed on Altera Corp.'s Cyclone series FPGA device EP1C6T144C8.