Design And Implementation Of Efficient Asynchronous FIFO

The asynchronous FIFO (First In First Out) is a first-in, first-out memory, Can achieve the transfer of data between different clock domains. The asynchronous FIFO scene is very extensive, not only to meet the different needs of the modern national defense and aerospace applications, can also be used in other areas such as data acquisition and image processing.Compared to synchronous integrated circuit design, asynchronous integrated circuits with low power consumption, the potential of high-performance and ease of modular design, the integrated circuit design has been used during the major company now. Between asynchronous clock domain data transmission in asynchronous IC design is a key issue, asynchronous FIFO is an important means to solve this problem.Empty/full signal generation and the metastability are the two difficulties in the design of asynchronous FIFO. First of all:Empty/Full signals are generated by comparing the read and write address pointer to produce, when the read and write address pointer is at the same time, the FIFO can not be sure in the empty state or state; Second:the metastable problem, due to read/write address under different clock domains, it needs to be synchronizing before comparing, due to the address pointer is over, in the synchronization process will inevitably produce metastable problem.Aiming at two problems, the design by using pointer to address additional bits and the gray code instead of the binary code address way to carry on the effective solution, namely in front of the read-write address to add one additional state is empty or full. Increased retention when empty definition of full state space (Reserve) this parameter, thus enhanced the stability of the FIFO. Using gray code address pointer instead of binary code, and uses a configurable synchronous circuit to solve this problem. Also through to reasonable use of FIFO clock, the clock stopped, if FIFO doesn’t work in read/write control module, the clock restarted work until it began to work, so as to meet the requirements of the high efficiency.The FIFO design module written in Verilog HDL code, and Synopsys VCS functional simulation for functional verification using Xilinx FPGA, due to the design of the FIFO module is a part of the voice processor division road module, so we put it with voice processorother modules of the road together, the SMIC0.18μm CMOS technology library synthesis and layout according to project needs and successful implementation of the chip tapeout. The test results show that:the voice processor calculation error less than4%; the average power consumption is about1.18mW/MHz on1.8V operating voltage, This design is expected to reach the requirement in the stability, power and speed.