Key Circuits Research And Design In A12-bit High-speed DAC

As one of the key components in the modern wireless communication system,the performance of Digital-to-Analog Converter （DAC） has an important impact onthe overall performance of the system. In recent years, with the rapid developmentof wireless communication technology, the performance requirements of the DACare higher and higher, especially reflected in terms of broadband and high-speed. Inorder to meet the demand, this thesis designed a high-speed high-precision DACwhich is based on the SMIC0.13μm3.3V CMOS technology. The thesis hastheoretical and realistic significance.The current mainstream structure of segmented current-steering was used inthe thesis. Based on the particular consideration of the DAC area, the overallperformance which is influenced by the staging point, finally, the design adopts5+4+3segmented structure. For the sake of achieving better balance between theperformance and area, the higher9bits （5+4） are used the Unary-Structure whilethe lower3bits used the Binary-Structure. The key circuits of the DAC which areincluding the current source array and its bias circuit, the thermometer decodingcircuit, the current source switch driving circuit, and the bandgap reference circuitare designed and simulated by the SMIC0.13μm3.3V CMOS technology. In orderto achieve good dynamic performance, the DAC’s current sources are used PMOScascode structure to achieve high output impedance at high frequency. In addition,for the purpose of restraining the influence of non-ideal factors, such as thenon-synchronized switch control signals, the effect of clock feed-through and thephenomenon of switch tube closed at the same time, the design introduced thesynchronization latches, reduced the switch control signal’s voltage amplitude andcross-point. Also, the thesis did some research on low-voltage current-steeringDAC design, and draw the conclusion of that the difficulty of low-voltage designmainly comes from the current source array, the reduction of output impedance willhave greater impact on SFDR performanceThe whole DAC circuit is designed and simulated by the Cadence spectresimulation software. Simulation results show that: for the static performance, theDAC output voltage curve is smooth and only has small glitches, DNL≈±0.7LSB,INL≈±1.7LSB; For the dynamic performance, at the highest sampling frequency f_sample=400MHz, when the input signal frequency f_vin=41.796875MHz, SFDR is ashigh as86.1dB and ENOB=11.93bit, when f_vin=159.765625MHz, SFDR is still72.5dB, ENOB=11.32bit. The DAC’s performance indicators have reached thedesign requirements.