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Gsps, Ultra-high-speed Adc System Design And Simulation

Posted on:2007-04-15Degree:MasterType:Thesis
Country:ChinaCandidate:L Y XiongFull Text:PDF
GTID:2208360185456120Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Driven by the requirements of an analog-to-digital converter (ADC) with excellent performances, ADCs have been made a rapid progress towards high speed, high resolution and low power dissipation. At present, communication receivers, disk read channels, and gigabit ethernet require the digitized received waveform to a resolution of 6-8b. Therefore, the study in ultrahigh speed ADCs with the relatively low resolution is an important research topic.Modeling and simulating the ADC system by adopting standard CMOS technologies can provide the theoretical supports for design and optimization of ultrahigh speed ADCs.In this dissertation, the generic high-speed ADC architectures was investigated and the block of the ultrahigh speed ADC was designed. Furthermore, the ADC system error model was simulated. The main contents are as follows:Firstly, two typical architectures of ultrahigh speed ADC are presented. Moreover, the block diagram design of a 6-bit 1GSample/s (GSPS) ADC is described. In the meantime, the building blocks and key ideas to improve the sampling rate are also described. There are three main problems in different building blocks that will impair the dynamic performance of ultrahigh speed ADC. They are offset, sampling time uncertainty and signal-dependent delay. Therefore, they serve as restricts to design these blocks at the circuit level.Secondly, based on the study of the resistor offset averaging network, a capacitance offset averaging network is designed. The differential non-linearity (DNL) and the integral non-linearity (INL) are reduced 70% by applying this capacitance offset averaging network. Different from the resistor offset averaging, the INL decreases more rapidly. The slope of INL is two more times than the slope of DNL. The capacitance offset averaging network is used in the distributed track-and-hold circuit block of the designed system.Finally, according to the analysis on error effects in ADC, the mathematics error model is simulated. Furthermore, the input-output characteristics including input-...
Keywords/Search Tags:ultrahigh speed analog-to-digital converter, offset averaging, modeling, simulating
PDF Full Text Request
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