Cmos High-speed Phase-locked Loop Design

In this paper , a clock recovery system that based on phase control technology is studied . The clock recovery block of USB2.0 Transceiver Macrocell consists of phase locked circuit , such as PLL and DLL ( Delay Locked Loop ) .This block use external crystal 12MHz sin signal to produce 60MHz , 120MHz , 480MHz clock signal , and can recover colock signal form date wave .It can support 480Mbps (HS) and 12Mbps(FS) word speeds as defined in USB2.0 Specification..When design deep sub-micrometer CMOS circuit, velocity , power and ship area are the main factors that should be considered . And should design proper circuit structure or then- mixed structure to meet the technical required .To produce high speed , robust clock signal is the aim of this research . The problem in high speed signal process , such as parasitic parameter and gate delay is also the difficulty hi the research.The clock recovery system is fabricated in TSMC 0.25um CMOS process. Simulation in SmartSpice shows that the circuit as expected.