.10 Bits The 100msps Pipelined Adc System Structure Optimization And Part Of Unit Design

Based on the requirements of communication systems with theories andapplications of high speed and high resolution ADC, the optimum structure of a10-bit 3.3V 100MSPS Pipelined CMOS ADC is obtained, while the partly key cellsof ADC are researched in detail how to design these circuits, such as the CMOSbootstrapped sampling switch ,the preamplifier-latch comparator and thetransconductance operation amplifier.Firstly, given a full consideration of the speed, power, area and dynamicperformance, the 3-stage, 3.5bit/stage structure is introduced. And digital correctioncircuits are added to diminish errors between stages. Secondly, some ADC basic circuits have been simulated with HSPICE simulatorin Cadence tools, using SMIC 0.35μm/3.3V CMOS process models. From thesimulation results, we can see that, all of the designed basic cells of this paper aresatisfied, compared with the specification, defined by the system of ADC. SFDR is70.6dB when Nyquist sampling sinusoid input signal applied.Finally, the layout of this chip is designed and checked, with SMIC 0.35μm 2P4Mmixed-signal CMOS process. Total die size of this ADC is 4.5*2.4mm2 and has 28pins in SOP package.As the result, by using these technologies, ADC can get 10-bit resolution and100MHz sampling speed. This ADC has already been completed and produced.Meanwhile, these technologies can be applied to video medium and digitalprocessing, too.